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? 2005 quicklogic corporation www.quicklogic.com ? 1 ? device highlights high performance & high density up to 60,000 usable pld gates with up to 316 i/os 300 mhz 16-bit counters, 400 mhz datapaths 0.35 m four-layer metal non-volatile cmos process for smallest die sizes easy to use/fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with 3.3 v and 5.0 v devices pci compliant with 3.3 v and 5.0 v buses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with individually controlled registered input path and output enables up to 316 i/o pins up to 308 bidirectional input/output pins, pci-compliant for 5.0 v and 3.3 v buses for -1/-2/-3/-4 speed grades up to eight high-drive input/distributed network pins up to eight low-skew distributed networks two array clock/control networks are available to the logic cell flip-flop; clock, set, and reset inputs ? each can be driven by an input-only pin up to six global clock/control networks are available to the logic cell; f1, clock, set, and reset inputs and the data input, i/o register clock, reset, and enable inputs as well as the output enable control ? each can be driven by an input- only pin, i/o pin, any logic cell output, or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz figure 1: up to 1,584 pasic 3 logic cells pasic 3 fpga family data sheet up to 60,000 usable pld gate pasic 3 fpga combining high performance and high density
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 2 table 1: pasic 3 product family members ql3004 ql3004e ql3006 ql3012 ql3025 ql3040 ql3060 max gates 5,188 5,188 8,008 15,740 32,616 48,384 75,232 logic array 8 x 12 8 x 12 10 x 16 20 x 16 28 x 24 36 x 28 44 x 36 logic cells 96 96 160 320 672 1,008 1,584 max flip-flops 178 178 322 438 876 1,260 1,900 max i/o 74 74 74 110 196 244 308 packages plcc 68 68 68 - - - - plcc 84 84 84 84 - - - tqfp 100 100 100 100 100 - - tqfp - - - 144 144 - - pqfp - - - - 208 208 208 pbga - - - - 256 - - pbga - - - - - 456 456 table 2: max i/o per device/package combination device 68 plcc 84 plcc 100 tqfp 144 tqfp 208 pqfp 256pbga 456 pbga ql3004 46 60 74 - - - - ql3004e 46 60 74 - - - - ql3006 46 60 74 - - - - ql3012 - 60 74 110 - - - ql3025 - - 74 110 166 196 - ql3040 - - - - 166 - 244 ql3060 - - - - 166 - 308
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 3 architecture overview the pasic 3 family of devices have a range of 4,000 to 60,000 usable pld gates. pasic 3 fpgas are fabricated on a 0.35 m four-layer metal process using quicklogic?s? pate nted vialink? technology to provide a unique combination of high performance, hi gh density, low cost, and extreme ease-of-use. the pasic 3 family of devices contain a range of 96 to 1,584 logic cells (see table 1 ). with a range of 74 to 316 i/os, the pasic 3 family is available in many device/package combinations (see table 2 ). software support for the complete pa sic 3 family is available throug h two basic packages. the turnkey quick works ? package provides the most complete fpga so ftware solution from design entry to logic synthesis, to place and route, to simulation. the quicktools tm for workstations package provides a solution for designers who use cadence ? , exemplar tm , mentor ? , synopsys ? , synplicity ? , viewlogic tm , aldec tm , or other third-party tools for design entry, synthesis, or simulation.
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 4 electrical specifications ac characteristics at v cc = 3.3 v, ta = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 9 by the numbers provided in table 3 through table 7 . table 3: logic cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagat ion delay over proc ess variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage, and temperature settings as specified in table 9 . 1 2 3 4 8 t pd combinatorial delay b b. these limits are derived fr om a representative selection of the slowest pa ths through the pasic 3 logic cell including typic al net delays. worst case delay values for specific paths should be determined from timing analys is of your particular design. 1.41.71.92.23.2 t su setup time b 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8 table 4: input-only/clock cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagati on delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage, and temperature settings as specified in table 9 . 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t lclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t lrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 5 figure 2: loads used for t pxz table 5: clock cells symbol parameter propagation delays (ns) loads per half column a a. the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, ea ch driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to eight l oads per half column. the global clock has up to 11 loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 table 6: input-only i/o cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagat ion delay over proc ess variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage, and temperature settings as specified in table 9 . 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t loclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t lorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 table 7: output-only i/o cells symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a a. the loads presented in figure 2 are used for t pxz : 2.0 - - - - t plz output delay low to tri-state 1.2 - - - - 1? 1? t phz t plz 5 pf 5 pf
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 6 dc characteristics the dc specifications are provided in table 8 through table 10 . table 8: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 4.6 v dc input current 20 ma v ccio voltage -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c table 9: operating range symbol parameter military industrial commercial unit min. max. min. max. min. max. v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade - - 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a table 10: dc characteristics symbol parameter conditions min . max . units v ih input high voltage 0.5 v cc v ccio +0.5 v v il input low voltage -0.5 0.3 v cc v v oh output high voltage ioh = -12 ma 2.4 v cc v ioh = -500 a 0.9 v cc v cc v v ol output low voltage iol = 16 ma a a. applies only to -1/-2/-3/-4 commercia l grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. 0.45 v iol = 1.5 ma 0.1 v cc v i i i or i/o input leakage current vi = v ccio or gnd -10 10 a i oz 3-state output leakage current vi = v ccio or gnd -10 10 a c i input capacitance b b. capacitance is sample tested only. clock pins are 12 pf maximum. 10 pf i os output short circuit current c c. only one output at a time. duration should not exceed 30 seconds. vo = gnd -15 -180 ma vo = v cc 40 210 ma i cc d.c. supply current d d. for -1/-2/-3/-4 commercial grade devices only. maximum i cc is 3 ma for -0 commercial grad e and all industrial grade devices and 5 ma for all military grade devices. fo r ac conditions, contact quicklogi c customer applications group (see ?contact information? on page 49 ). vi, vio = v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio 0 100 a
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 7 kv and kt graphs figure 3: voltage factor vs. supply voltage figure 4: temperature factor vs. operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 8 power-up sequencing figure 5: power-up requirements when powering up a device, the v cc /v ccio rails must take 400 s or long er to reach the maximum value (refer to figure 5 ). note: ramping v cc /v ccio to the maximum voltage faster than 400 s can cause the device to behave improperly. for users with a limited power budget, keep (v ccio -v cc ) max 500 mv when ramping up the power supply. voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 9 jtag figure 6: jtag block diagram microprocessors and application specific integrated ci rcuits (asics) pose many design challenges, not the least of which concerns the accessibilit y of test points. the joint test acce ss group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir); these allow users to run thre e required tests, along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload in struction), and input boundary cells capture the input data for analysis. sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 10 bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypa ss register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device withou t affecting the operation of the device. pin descriptions table 11: pin descriptions pin function description tdi test data in for jtag hold high during normal operation. connect to v cc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. v cc power supply pin connect to 3.3 v supply. v ccio input voltage tolerance pin connect to 5.0 v supply if 5.0 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground.
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 11 ql3004 ? 68 plcc pinout diagram figure 7: ql3004 ? 68 pin plcc (top view) ql3004 ? 68 plcc pinout table table 12: ql3004 ? 68 plcc pinout table 68 plcc function 68 plcc function 68 plcc function 68 plcc function 1 gnd 18 vcc 35 gnd 52 vcc 2 i/o 19 gclk/i 36 i/o 53 gclk/i 3 i/o 20 gclk/i 37 i/o 54 gclk/i 4 vccio 21 i/o 38 i/o 55 i/o 5 i/o 22 i/o 39 vccio 56 i/o 6 i/o 23 i/o 40 i/o 57 i/o 7 i/o 24 i/o 41 i/o 58 i/o 8 i/o 25 i/o 42 trstb 58 i/o 9 tdo 26 i/o 43 tms 60 i/o 10 i/o 27 tdi 44 i/o 61 tck 11 i/o 28 i/o 45 i/o 62 stm 12 i/o 29 i/o 46 i/o 63 i/o 13 i/o 30 i/o 47 i/o 64 i/o 14 gnd 31 i/o 48 gnd 65 i/o 15 i/o 32 i/o 49 i/o 66 i/o 16 gclk/i 33 i/o 50 gclk/i 67 i/o 17 aclk/i 34 i/o 51 aclk/i 68 i/o tdo io io io io vccio io io gnd io io io io io io stm tck io io io io io io gclk/i gclk/i vcc aclk/i gclk/i io gnd io io io io tdi io io io io io io io gnd io io io vccio io io trstb tms 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ql3004-1pl68c pasic 3 io io io io gnd io gclk/i aclk/i vcc gclk/i gclk/i io io io io io io 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 12 ql3004 ? 84 plcc pinout diagram figure 8: ql3004 ? 84 pin plcc (top view) ql3004 ? 84 plcc pinout table table 13: ql3004 ? 84 plcc pinout table 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 vccio 25 vcc 46 vccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 trstb 73 i/o 11 tdo 32 i/o 53 tms 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 stm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 vcc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 vcc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3004-1pl84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 13 ql3004 ? 100 tqfp pinout diagram figure 9: ql3004 ? 100 pin tqfp (top view) ql3004 ? 100 tqfp pinout table table 14: ql3004 ? 100 tqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 gclk/i 36 i/o 61 gclk/i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 gclk/i 39 i/o 64 gclk/i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo pin 1 pin 26 pin 51 pin 76 ql3004-1pf100c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 14 ql3004e ? 68 plcc pinout diagram figure 10: ql3004e ? 68 pin plcc (top view) ql3004e ? 68 plcc pinout table table 15: ql3004e ? 68 plcc pinout table 68 plcc function 68 plcc function 68 plcc function 68 plcc function 1 gnd 18 vcc 35 gnd 52 vcc 2 i/o 19 i 36 i/o 53 i 3 i/o 20 gclk/i 37 i/o 54 gclk/i 4 vccio 21 i/o 38 i/o 55 i/o 5 i/o 22 i/o 39 vccio 56 i/o 6 i/o 23 i/o 40 i/o 57 i/o 7 i/o 24 i/o 41 i/o 58 i/o 8 i/o 25 i/o 42 trstb 58 i/o 9 tdo 26 i/o 43 tms 60 i/o 10 i/o 27 tdi 44 i/o 61 tck 11 i/o 28 i/o 45 i/o 62 stm 12 i/o 29 i/o 46 i/o 63 i/o 13 i/o 30 i/o 47 i/o 64 i/o 14 gnd 31 i/o 48 gnd 65 i/o 15 i/o 32 i/o 49 i/o 66 i/o 16 i 33 i/o 50 i 67 i/o 17 aclk/i 34 i/o 51 aclk/i 68 i/o tdo io io io io vccio io io gnd io io io io io io stm tck io io io io io io gclk/i gclk/i vcc aclk/i gclk/i io gnd io io io io tdi io io io io io io io gnd io io io vccio io io trstb tms 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ql3004e-1pl68c pasic 3 io io io io gnd io gclk/i aclk/i vcc gclk/i gclk/i io io io io io io 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 15 ql3004e ? 84 plcc pinout diagram figure 11: ql3004e ? 84 pin plcc (top view) ql3004e ? 84 plcc pinout table table 16: ql3004e ? 84 plcc pinout table 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 vccio 25 vcc 46 vccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 trstb 73 i/o 11 tdo 32 i/o 53 tms 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 stm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 vcc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 vcc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3004e-1pl84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 16 ql3004e ? 100 tqfp pinout diagram figure 12: ql3004e ? 100 pin tqfp (top view) ql3004e ? 100 tqfp pinout table table 17: ql3004e ? 100 tqfp pinout table 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo pin 1 pin 26 pin 51 pin 76 ql3004e-1pf100c pasic 3
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 17 ql3006 ? 68 plcc pinout diagram figure 13: ql3006 ? 68-pin plcc (top view) ql3006 ? 68 plcc pinout table table 18: ql3006 ? 68 plcc pinout table 68 plcc function 68 plcc function 68 plcc function 68 plcc function 1 gnd 18 vcc 35 gnd 52 vcc 2 i/o 19 i 36 i/o 53 i 3 i/o 20 gclk/i 37 i/o 54 gclk/i 4 vccio 21 i/o 38 i/o 55 i/o 5 i/o 22 i/o 39 vccio 56 i/o 6 i/o 23 i/o 40 i/o 57 i/o 7 i/o 24 i/o 41 i/o 58 i/o 8 i/o 25 i/o 42 trstb 58 i/o 9 tdo 26 i/o 43 tms 60 i/o 10 i/o 27 tdi 44 i/o 61 tck 11 i/o 28 i/o 45 i/o 62 stm 12 i/o 29 i/o 46 i/o 63 i/o 13 i/o 30 i/o 47 i/o 64 i/o 14 gnd 31 i/o 48 gnd 65 i/o 15 i/o 32 i/o 49 i/o 66 i/o 16 i 33 i/o 50 i 67 i/o 17 aclk/i 34 i/o 51 aclk/i 68 i/o tdo io io io io vccio io io gnd io io io io io io stm tck io io io io io io gclk/i i vcc aclk/i i io gnd io io io io tdi io io io io io io io gnd io io io vccio io io trstb tms 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ql3006-1pl68c pasic 3 io io io io gnd io i aclk/i vcc i gclk/i io io io io io io 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 18 ql3006 ? 84 plcc pinout diagram figure 14: ql3006 ? 84 pin plcc (top view) ql3006 ? 84 plcc pinout table table 19: ql3006 ? 84 plcc pinout table 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 vccio 25 vcc 46 vccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 trstb 73 i/o 11 tdo 32 i/o 53 tms 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 stm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 vcc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 vcc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3006-1pl84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 19 ql3006 ? 100 tqfp pinout diagram figure 15: ql3006 ? 100 pin tqfp (top view) ql3006 ? 100 tqfp pinout table table 20: ql3006 ? 100 tqfp pinout table 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo pin 1 pin 26 pin 51 pin 76 ql3006-1pf100c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 20 ql3012 ? 84 plcc pinout diagram figure 16: ql3012 ? 84 pin plcc (top view) ql3012 ? 84 plcc pinout table table 21: ql3012 ? 84 plcc pinout table 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 vccio 25 vcc 46 vccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 trstb 73 i/o 11 tdo 32 i/o 53 tms 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 stm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 vcc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 vcc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3012-1pl84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 21 ql3012 ? 100 tqfp pinout diagram figure 17: ql3012 ? 100 pin tqfp (top view) ql3012 ? 100 tqfp pinout table table 22: ql3012 ? 100 tqfp pinout table 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo pin 1 pin 26 pin 51 pin 76 ql3012-1pf100c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 22 ql3012 ? 144 tqfp pinout diagram figure 18: ql3012 ? 144 pin tqfp (top view) pin 1 pin 37 pin 73 pin 109 ql3012-1pf144c pasic 3
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 23 ql3012 ? 144 tqfp pinout table table 23: ql3012 ? 144 tqfp pinout table 144 tqfp function 144 tqfp function 144 tqfp function 144 tqfp function 1 i/o 38 tdi 75 i/o 111 i/o 2 i/o 39 i/o 76 i/o 112 i/o 3 i/o 40 i/o 77 i/o 113 i/o 4 i/o 41 i/o 78 i/o 114 vcc 5 i/o 42 vcc 79 vcc 115 i/o 6 i/o 43 i/o 80 i/o 116 i/o 7 vcc 44 i/o 81 i/o 117 i/o 8 i/o 45 i/o 82 i/o 118 i/o 9 i/o 46 i/o 83 i/o 119 i/o 10 i/o 47 i/o 84 i/o 120 i/o 11 i/o 48 i/o 85 i/o 121 i/o 12 i/o 49 i/o 86 i/o 122 gnd 13 i/o 50 gnd 87 gnd 123 i/o 14 i/o 51 i/o 88 i/o 124 i/o 15 gnd 52 i/o 89 i 125 i/o 16 i/o 53 i/o 90 aclk/i 126 gnd 17 i 54 gnd 91 vcc 127 i/o 18 aclk/i 55 i/o 92 i 128 i/o 19 vcc 56 i/o 93 gclk/i 129 i/o 20 i 57 i/o 94 vcc 130 vccio 21 gclk/i 58 vccio 95 i/o 131 i/o 22 vcc 59 i/o 96 i/o 132 i/o 23 i/o 60 i/o nc i/o 133 i/o 24 i/o 61 i/o 97 i/o 134 i/o 25 i/o 62 i/o 98 i/o 135 i/o 26 i/o 63 i/o 99 i/o 136 i/o 27 i/o 64 i/o 100 i/o nc i/o 28 i/o 65 i/o 101 i/o 137 i/o 29 i/o 66 gnd 102 gnd 138 gnd 30 gnd 67 i/o 103 i/o 139 i/o 31 i/o 68 i/o 104 i/o 140 i/o 32 i/o 69 i/o 105 i/o 141 i/o 33 i/o 70 i/o 106 i/o 142 i/o 34 i/o 71 trstb 107 i/o 143 tdo 35 i/o 72 tms 108 i/o 144 i/o 36 i/o 73 i/o 109 tck 37 i/o 74 i/o 110 stm
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 24 ql3025 ? 100 tqfp pinout diagram figure 19: ql3025 ? 100 pin tqfp (top view) ql3025 ? 100 tqfp pinout table table 24: ql3025 ? 100 tqfp pinout table 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk/i 37 i/o 62 aclk/i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk/i 40 i/o 65 gclk/i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo pin 1 pin 26 pin 51 pin 76 ql3025-1pf100c pasic 3
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 25 ql3025 ? 144 tqfp pinout diagram figure 20: ql3025 ? 144 pin tqfp (top view) pin 1 pin 37 pin 73 pin 109 ql3025-1pf144c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 26 ql3025 ? 144 tqfp pinout table table 25: ql3025 ? 144 tqfp pinout table 144 tqfp function 144 tqfp function 144 tqfp function 144 tqfp function 144 tqfp function 144 tqfp function 1 i/o 25 i/o 49 i/o 73 i/o 97 i/o 121 i/o 2 i/o 26 i/o 50 gnd 74 i/o 98 i/o 122 gnd 3 i/o 27 i/o 51 i/o 75 i/o 99 i/o 123 i/o 4 i/o 28 i/o 52 i/o 76 i/o 100 i/o 124 i/o 5 i/o 29 i/o 53 i/o 77 i/o 101 i/o 125 i/o 6 i/o 30 gnd 54 gnd 78 i/o 102 gnd 126 gnd 7 vcc 31 i/o 55 i/o 79 vcc 103 i/o 127 i/o 8 i/o 32 i/o 56 i/o 80 i/o 104 i/o 128 i/o 9 i/o 33 i/o 57 i/o 81 i/o 105 i/o 129 i/o 10 i/o 34 i/o 58 vccio 82 i/o 106 i/o 130 vccio 11 i/o 35 i/o 59 i/o 83 i/o 107 i/o 131 i/o 12 i/o 36 i/o 60 i/o 84 i/o 108 i/o 132 i/o 13 i/o 37 i/o 61 i/o 85 i/o 109 tck 133 i/o 14 i/o 38 tdi 62 i/o 86 i/o 110 stm 134 i/o 15 gnd 39 i/o 63 i/o 87 gnd 111 i/o 135 i/o 16 i/o 40 i/o 64 i/o 88 i/o 112 i/o 136 i/o 17 i 41 i/o 65 i/o 89 i 113 i/o 137 i/o 18 aclk/i 42 vcc 66 gnd 90 aclk/i 114 v cc 138 gnd 19 vcc 43 i/o 67 i/o 91 vcc 115 i/o 139 i/o 20 i 44 i/o 68 i/o 92 i 116 i/o 140 i/o 21 gclk/i 45 i/o 69 i/o 93 gclk/i 117 i/o 141 i/o 22 vcc 46 i/o 70 i/o 94 vcc 118 i/o 142 i/o 23 i/o 47 i/o 71 trstb 95 i/o 119 i/o 143 tdo 24 i/o 48 i/o 72 tms 96 i/o 120 i/o 144 i/o
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 27 ql3025 ? 208 pqfp pinout diagram figure 21: ql3025 ? 208 pin pqfp (top view) pin 1 pin 53 pin 105 pin 157 ql3025-1pq208c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 28 ql3025 ? 208 pqfp pinout table table 26: ql3025 ? 208 pqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 1 i/o 43 gnd 85 i/o 127 gnd 169 i/o 2 i/o 44 i/o 86 i/o 128 i/o 170 i/o 3 i/o 45 i/o 87 i/o 129 i 171 i/o 4 i/o 46 i/o 88 i/o 130 aclk/i 172 i/o 5 i/o 47 i/o 89 i/o 131 vcc 173 i/o 6 i/o 48 i/o 90 i/o 132 i 174 i/o 7 i/o 49 i/o 91 i/o 133 gclk/i 175 i/o 8 i/o 50 i/o 92 i/o 134 v cc 176 i/o 9 i/o 51 i/o 93 i/o 135 i/o 177 gnd 10 vcc 52 i/o 94 i/o 136 i/o 178 i/o 11 i/o 53 i/o 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 i/o 138 i/o 180 i/o 13 i/o 55 i/o 97 vcc 139 i/o 181 i/o 14 i/o 56 i/o 98 i/o 140 i/o 182 gnd 15 i/o 57 i/o 99 i/o 141 i/o 183 i/o 16 i/o 58 i/o 100 i/o 142 i/o 184 i/o 17 i/o 59 gnd 101 i/o 143 i/o 185 i/o 18 i/o 60 i/o 102 i/o 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 i/o 104 tms 146 i/o 188 i/o 21 i/o 63 i/o 105 i/o 147 gnd 189 i/o 22 i/o 64 i/o 106 i/o 148 i/o 190 i/o 23 gnd 65 i/o 107 i/o 149 i/o 191 i/o 24 i/o 66 i/o 108 i/o 150 i/o 192 i/o 25 i 67 i/o 109 i/o 151 i/o 193 i/o 26 aclk/i 68 i/o 110 i/o 152 i/o 194 i/o 27 vcc 69 i/o 111 i/o 153 i/o 195 i/o 28 i 70 i/o 112 i/o 154 i/o 196 i/o 29 gclk/i 71 i/o 113 i/o 155 i/o 197 i/o 30 vcc 72 i/o 114 vcc 156 i/o 198 i/o 31 i/o 73 gnd 115 i/o 157 tck 199 gnd 32 i/o 74 i/o 116 gnd 158 stm 200 i/o 33 i/o 75 i/o 117 i/o 159 i/o 201 vcc 34 i/o 76 i/o 118 i/o 160 i/o 202 i/o 35 i/o 77 i/o 119 i/o 161 i/o 203 i/o 36 i/o 78 gnd 120 i/o 162 i/o 204 i/o 37 i/o 79 i/o 121 i/o 163 gnd 205 i/o 38 i/o 80 i/o 122 i/o 164 i/o 206 i/o 39 i/o 81 i/o 123 i/o 165 vcc 207 tdo 40 i/o 82 i/o 124 i/o 166 i/o 208 i/o 41 vcc 83 vccio 125 i/o 167 i/o 42 i/o 84 i/o 126 i/o 168 i/o
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 29 ql3025 ? 256 pbga pinout diagram figure 22: ql3025 ? 256-pin pbga pinout diagram ql3025-1pb256c pasic 3 bottom view top view pin a1 corner 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 30 ql3025 ? 256 pbga pinout table table 27: ql3025 ? 256 pbga pinout table 256 pbga function 256 pbga function 256 pbga function 256 pbga function 256 pbga function 256 pbga function a1 vss c4 i/o e19 i/o l2 aclk/i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 i t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk/i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 i/o a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 i/o a8 i/o c11 i/o f18 nc m1 i/o u4 vss w7 i/o a9 i/o c12 i/o f19 i/o m2 i/o u5 i/o w8 i/o a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 i/o a11 i/o c14 i/o g1 i/o m4 nc u7 i/o w10 i/o a12 i/o c15 i/o g2 nc m17 nc u8 vss w11 i/o a13 i/o c16 i/o g3 i/o m18 i/o u9 i/o w12 i/o a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 i/o a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 i/o a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 i/o a17 i/o c20 i/o g19 nc n2 i/o u13 vss w16 i/o a18 i/o d1 i/o g20 i/o n3 i/o u14 i/o w17 i/o a19 tck d2 i/o h1 i/o n4 vss u15 vcc w18 i/o a20 i/o d3 i/o h2 i/o n17 vss u16 i/o w19 i/o b1 tdo d4 vss h3 i/o n18 i/o u17 vss w20 trstb b2 i/o d5 i/o h4 vss n19 i/o u18 i/o y1 i/o b3 i/o d6 vcc h17 vss n20 i/o u19 i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 vss h19 i/o p2 i/o v1 i/o y4 i/o b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 i/o b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 i/o b8 i/o d11 vcc j2 i/o p17 i/o v4 i/o y7 i/o b9 i/o d12 i/o j3 nc p18 i/o v5 i/o y8 i/o b10 i/o d13 vss j4 i/o p19 nc v6 i/o y9 i/o b11 i/o d14 i/o j17 nc p20 i/o v7 i/o y10 i/o b12 i/o d15 vcc j18 i/o r1 nc v8 i/o y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 i/o y12 i/o b14 i/o d17 vss j20 gclk/i r3 i/o v10 i/o y13 i/o b15 i/o d18 i/o k1 i/o r4 vcc v11 i/o y14 i/o b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 i/o b17 nc d20 i/o k3 i/o r18 i/o v13 i/o y16 i/o b18 stm e1 nc k4 vcc r19 i/o v14 i/o y17 i/o b19 nc e2 i/o k17 i r20 i/o v15 i/o y18 i/o b20 i/o e3 i/o k18 aclk/i t1 nc v16 i/o y19 i/o c1 i/o e4 i/o k19 i t2 i/o v17 i/o y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 i t4 nc v19 tms
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 31 ql3040 ? 208 pqfp pinout diagram figure 23: ql3040 ? 208 pin pqfp (top view) pin 1 pin 53 pin 105 pin 157 ql3040-1pq208c pasic 3
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 32 ql3040 ? 208 pqfp pinout table table 28: ql3040 ? 208 pqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 1 i/o 43 gnd 85 i/o 127 gnd 169 i/o 2 i/o 44 i/o 86 i/o 128 i/o 170 i/o 3 i/o 45 i/o 87 i/o 129 gclk/i 171 i/o 4 i/o 46 i/o 88 i/o 130 aclk/i 172 i/o 5 i/o 47 i/o 89 i/o 131 vcc 173 i/o 6 i/o 48 i/o 90 i/o 132 gclk/i 174 i/o 7 i/o 49 i/o 91 i/o 133 gclk/i 175 i/o 8 i/o 50 i/o 92 i/o 134 vcc 176 i/o 9 i/o 51 i/o 93 i/o 135 i/o 177 gnd 10 vcc 52 i/o 94 i/o 136 i/o 178 i/o 11 i/o 53 i/o 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 i/o 138 i/o 180 i/o 13 i/o 55 i/o 97 vcc 139 i/o 181 i/o 14 i/o 56 i/o 98 i/o 140 i/o 182 gnd 15 i/o 57 i/o 99 i/o 141 i/o 183 i/o 16 i/o 58 i/o 100 i/o 142 i/o 184 i/o 17 i/o 59 gnd 101 i/o 143 i/o 185 i/o 18 i/o 60 i/o 102 i/o 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 i/o 104 tms 146 i/o 188 i/o 21 i/o 63 i/o 105 i/o 147 gnd 189 i/o 22 i/o 64 i/o 106 i/o 148 i/o 190 i/o 23 gnd 65 i/o 107 i/o 149 i/o 191 i/o 24 i/o 66 i/o 108 i/o 150 i/o 192 i/o 25 gclk/i 67 i/o 109 i/o 151 i/o 193 i/o 26 aclk/i 68 i/o 110 i/o 152 i/o 194 i/o 27 v cc 69 i/o 111 i/o 153 i/o 195 i/o 28 gclk/i 70 i/o 112 i/o 154 i/o 196 i/o 29 gclk/i 71 i/o 113 i/o 155 i/o 197 i/o 30 v cc 72 i/o 114 v cc 156 i/o 198 i/o 31 i/o 73 gnd 115 i/o 157 tck 199 gnd 32 i/o 74 i/o 116 gnd 158 stm 200 i/o 33 i/o 75 i/o 117 i/o 159 i/o 201 v cc 34 i/o 76 i/o 118 i/o 160 i/o 202 i/o 35 i/o 77 i/o 119 i/o 161 i/o 203 i/o 36 i/o 78 gnd 120 i/o 162 i/o 204 i/o 37 i/o 79 i/o 121 i/o 163 gnd 205 i/o 38 i/o 80 i/o 122 i/o 164 i/o 206 i/o 39 i/o 81 i/o 123 i/o 165 v cc 207 tdo 40 i/o 82 i/o 124 i/o 166 i/o 208 i/o 41 v cc 83 v ccio 125 i/o 167 i/o 42 i/o 84 i/o 126 i/o 168 i/o
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 33 ql3040 ? 456 pbga pinout diagram figure 24: ql3040 ? 456-pin pbga pinout diagram ql3040-1pb456c pasic 3 bottom view top view pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 34 ql3040 ? 456 pbga pinout table table 29: ql3040 ? 456 pbga pinout table 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 nc m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 nc m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 nc c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 nc c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 nc c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 nc e16 gnd k1 nc n15 gnd/therm a19 i/o c18 nc e17 nc k2 nc n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 nc c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 nc c22 i/o e21 vcc k22 gnd n25 nc a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 nc p2 i/o b1 i/o c26 nc e25 i/o k26 i/o p3 nc b2 nc d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 nc d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 nc d4 gnd f3 nc l4 i/o p12 gnd/therm b6 nc d5 nc f4 nc l5 nc p13 gnd/therm b7 nc d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 nc d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 nc d9 gnd f24 i/o l14 gnd/therm p22 nc b11 nc d10 i/o f25 i/o l15 gnd/therm p23 gclk/i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk/i b13 i/o d12 gnd g1 i/o l22 nc p25 nc b14 nc d13 i/o g2 i/o l23 i/o p26 aclk/i b15 i/o d14 i/o g3 i/o l24 i/o r1 nc b16 i/o d15 gnd g4 i/o l25 nc r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk/i r4 nc b19 i/o d18 gnd g23 nc m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 nc g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 nc d22 i/o h1 nc m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 nc m13 gnd/therm r16 gnd/therm
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 35 r22 vcc w1 i/o ab12 nc ad1 i/o ae16 i/o r23 nc w2 i/o ab13 i/o ad2 nc ae17 i/o r24 nc w3 i/o ab14 gnd ad3 i/o ae18 i/o r25 i/o w4 i/o ab15 vcc ad4 i/o ae19 i/o r26 gclk/i w5 nc ab16 i/o ad5 i/o ae20 i/o t1 i/o w22 nc ab17 nc ad6 i/o ae21 i/o t2 i/o w23 i/o ab18 vcc ad7 i/o ae22 nc t3 i/o w24 i/o ab19 gnd ad8 i/o ae23 nc t4 i/o w25 i/o ab20 nc ad9 nc ae24 tms t5 vcc w26 nc ab21 vcc ad10 i/o ae25 i/o t11 gnd/thermal y1 nc ab22 gnd ad11 nc ae26 i/o t12 gnd/thermal y2 i/o ab23 i/o ad12 i/o af1 i/o t13 gnd/thermal y3 nc ab24 nc ad13 i/o af2 nc t14 gnd/thermal y4 i/o ab25 i/o ad14 i/o af3 i/o t15 gnd/thermal y5 i/o ab26 i/o ad15 i/o af4 nc t16 gnd/thermal y22 gnd ac1 i/o ad16 i/o af5 i/o t22 gnd y23 i/o ac2 i/o ad17 i/o af6 i/o t23 i/o y24 nc ac3 nc ad18 i/o af7 i/o t24 i/o y25 i/o ac4 gnd ad19 nc af8 i/o t25 nc y26 i/o ac5 nc ad20 nc af9 i/o t26 i/o aa1 i/o ac6 nc ad21 i/o af10 i/o u1 nc aa2 i/o ac7 nc ad22 i/o af11 nc u2 i/o aa3 nc ac8 nc ad23 trstb af12 i/o u3 i/o aa4 nc ac9 nc ad24 nc af13 i/o u4 i/o aa5 vcc ac10 nc ad25 i/o af14 nc u5 gnd aa22 vcc ac11 i/o ad26 i/o af15 nc u22 nc aa23 nc ac12 nc ae1 tdi af16 i/o u23 i/o aa24 i/o ac13 i/o ae2 i/o af17 i/o u24 i/o aa25 i/o ac14 vccio ae3 i/o af18 i/o u25 i/o aa26 i/o ac15 nc ae4 i/o af19 nc u26 i/o ab1 nc ac16 nc ae5 i/o af20 i/o v1 i/o ab2 i/o ac17 nc ae6 i/o af21 i/o v2 i/o ab3 i/o ac18 nc ae7 i/o af22 i/o v3 nc ab4 i/o ac19 i/o ae8 i/o af23 i/o v4 nc ab5 gnd ac20 i/o ae9 i/o af24 i/o v5 nc ab6 vcc ac21 i/o ae10 i/o af25 i/o v22 gnd ab7 nc ac22 nc ae11 i/o af26 i/o v23 nc ab8 nc ac23 gnd ae12 i/o v24 i/o ab9 nc ac24 nc ae13 i/o v25 nc ab10 vcc ac25 i/o ae14 i/o v26 i/o ab11 gnd ac26 i/o ae15 i/o table 29: ql3040 ? 456 pbga pinout table (continued) 456 function 456 function 456 function 456 function 456 function
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 36 ql3060 ? 208 pqfp pinout diagram figure 25: ql3060 ? 208 pin pqfp (top view) pin 1 pin 53 pin 105 pin 157 ql3060-1pq208c pasic 3
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 37 ql3060 ? 208 pqfp pinout table table 30: ql3060 ? 208 pqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 1 i/o 43 gnd 85 i/o 127 gnd 169 i/o 2 i/o 44 i/o 86 i/o 128 i/o 170 i/o 3 i/o 45 i/o 87 i/o 129 gclk/i 171 i/o 4 i/o 46 i/o 88 i/o 130 aclk/i 172 i/o 5 i/o 47 i/o 89 i/o 131 vcc 173 i/o 6 i/o 48 i/o 90 i/o 132 gclk/i 174 i/o 7 i/o 49 i/o 91 i/o 133 gclk/i 175 i/o 8 i/o 50 i/o 92 i/o 134 vcc 176 i/o 9 i/o 51 i/o 93 i/o 135 i/o 177 gnd 10 vcc 52 i/o 94 i/o 136 i/o 178 i/o 11 i/o 53 i/o 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 i/o 138 i/o 180 i/o 13 i/o 55 i/o 97 v cc 139 i/o 181 i/o 14 i/o 56 i/o 98 i/o 140 i/o 182 gnd 15 i/o 57 i/o 99 i/o 141 i/o 183 i/o 16 i/o 58 i/o 100 i/o 142 i/o 184 i/o 17 i/o 59 gnd 101 i/o 143 i/o 185 i/o 18 i/o 60 i/o 102 i/o 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 i/o 104 tms 146 i/o 188 i/o 21 i/o 63 i/o 105 i/o 147 gnd 189 i/o 22 i/o 64 i/o 106 i/o 148 i/o 190 i/o 23 gnd 65 i/o 107 i/o 149 i/o 191 i/o 24 i/o 66 i/o 108 i/o 150 i/o 192 i/o 25 gclk/i 67 i/o 109 i/o 151 i/o 193 i/o 26 aclk/i 68 i/o 110 i/o 152 i/o 194 i/o 27 vcc 69 i/o 111 i/o 153 i/o 195 i/o 28 gclk/i 70 i/o 112 i/o 154 i/o 196 i/o 29 gclk/i 71 i/o 113 i/o 155 i/o 197 i/o 30 vcc 72 i/o 114 vcc 156 i/o 198 i/o 31 i/o 73 gnd 115 i/o 157 tck 199 gnd 32 i/o 74 i/o 116 gnd 158 stm 200 i/o 33 i/o 75 i/o 117 i/o 159 i/o 201 vcc 34 i/o 76 i/o 118 i/o 160 i/o 202 i/o 35 i/o 77 i/o 119 i/o 161 i/o 203 i/o 36 i/o 78 gnd 120 i/o 162 i/o 204 i/o 37 i/o 79 i/o 121 i/o 163 gnd 205 i/o 38 i/o 80 i/o 122 i/o 164 i/o 206 i/o 39 i/o 81 i/o 123 i/o 165 vcc 207 tdo 40 i/o 82 i/o 124 i/o 166 i/o 208 i/o 41 vcc 83 vccio 125 i/o 167 i/o 42 i/o 84 i/o 126 i/o 168 i/o
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 38 ql3060 ? 456 pbga pinout diagram figure 26: ql3060 ? 456-pin pbga pinout diagram ql3060-1pb456c pasic 3 bottom view top view pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 39 ql3060 ? 456 pbga pinout table table 31: ql3060 ? 456 pbga pinout table 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 i/o m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 i/o m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 i/o c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 i/o c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 i/o c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 i/o e16 gnd k1 i/o n15 gnd/therm a19 i/o c18 i/o e17 nc k2 i/o n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 i/o c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 i/o c22 i/o e21 vcc k22 gnd n25 i/o a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 i/o p2 i/o b1 i/o c26 i/o e25 i/o k26 i/o p3 i/o b2 i/o d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 i/o d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 i/o d4 gnd f3 i/o l4 i/o p12 gnd/therm b6 i/o d5 i/o f4 nc l5 nc p13 gnd/therm b7 i/o d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 i/o d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 i/o d9 gnd f24 i/o l14 gnd/therm p22 nc b11 i/o d10 i/o f25 i/o l15 gnd/therm p23 gclk/i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk/i b13 i/o d12 gnd g1 i/o l22 nc p25 i/o b14 i/o d13 i/o g2 i/o l23 i/o p26 aclk/i b15 i/o d14 i/o g3 i/o l24 i/o r1 i/o b16 i/o d15 gnd g4 i/o l25 i/o r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk/i r4 nc b19 i/o d18 gnd g23 i/o m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 i/o g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 i/o d22 i/o h1 i/o m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 i/o m13 gnd/therm r16 gnd/therm
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 40 r22 vcc w1 i/o ab12 nc ad1 i/o ae16 i/o r23 nc w2 i/o ab13 i/o ad2 nc ae17 i/o r24 i/o w3 i/o ab14 gnd ad3 i/o ae18 i/o r25 i/o w4 i/o ab15 vcc ad4 i/o ae19 i/o r26 gclk/i w5 nc ab16 i/o ad5 i/o ae20 i/o t1 i/o w22 nc ab17 nc ad6 i/o ae21 i/o t2 i/o w23 i/o ab18 vcc ad7 i/o ae22 i/o t3 i/o w24 i/o ab19 gnd ad8 i/o ae23 nc t4 i/o w25 i/o ab20 nc ad9 i/o ae24 tms t5 vcc w26 i/o ab21 vcc ad10 i/o ae25 i/o t11 gnd/thermal y1 i/o ab22 gnd ad11 i/o ae26 i/o t12 gnd/thermal y2 i/o ab23 i/o ad12 i/o af1 i/o t13 gnd/thermal y3 i/o ab24 i/o ad13 i/o af2 i/o t14 gnd/thermal y4 i/o ab25 i/o ad14 i/o af3 i/o t15 gnd/thermal y5 i/o ab26 i/o ad15 i/o af4 i/o t16 gnd/thermal y22 gnd ac1 i/o ad16 i/o af5 i/o t22 gnd y23 i/o ac2 i/o ad17 i/o af6 i/o t23 i/o y24 i/o ac3 nc ad18 i/o af7 i/o t24 i/o y25 i/o ac4 gnd ad19 i/o af8 i/o t25 i/o y26 i/o ac5 i/o ad20 i/o af9 i/o t26 i/o aa1 i/o ac6 nc ad21 i/o af10 i/o u1 i/o aa2 i/o ac7 i/o ad22 i/o af11 i/o u2 i/o aa3 nc ac8 i/o ad23 trstb af12 i/o u3 i/o aa4 nc ac9 nc ad24 i/o af13 i/o u4 i/o aa5 vcc ac10 i/o ad25 i/o af14 i/o u5 gnd aa22 vcc ac11 i/o ad26 i/o af15 i/o u22 nc aa23 nc ac12 nc ae1 tdi af16 i/o u23 i/o aa24 i/o ac13 i/o ae2 i/o af17 i/o u24 i/o aa25 i/o ac14 vccio ae3 i/o af18 i/o u25 i/o aa26 i/o ac15 nc ae4 i/o af19 i/o u26 i/o ab1 i/o ac16 i/o ae5 i/o af20 i/o v1 i/o ab2 i/o ac17 i/o ae6 i/o af21 i/o v2 i/o ab3 i/o ac18 nc ae7 i/o af22 i/o v3 i/o ab4 i/o ac19 i/o ae8 i/o af23 i/o v4 nc ab5 gnd ac20 i/o ae9 i/o af24 i/o v5 nc ab6 vcc ac21 i/o ae10 i/o af25 i/o v22 gnd ab7 nc ac22 nc ae11 i/o af26 i/o v23 nc ab8 nc ac23 gnd ae12 i/o v24 i/o ab9 nc ac24 i/o ae13 i/o v25 i/o ab10 vcc ac25 i/o ae14 i/o v26 i/o ab11 gnd ac26 i/o ae15 i/o table 31: ql3060 ? 456 pbga pinout table (continued) 456 function 456 function 456 function 456 function 456 function
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 41 package mechanical drawings 68 plcc packaging drawing
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 42 84 plcc packaging drawing
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 43 100 tqfp mechanical drawing
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 44 144 tqfp mechanical drawing
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 45 208 pqfp packaging drawing
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 46 256 pbga mechanical drawing
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 47 456 pbga mechanical drawing
www.quicklogic.com ? 2005 quicklogic corporation pasic 3 fpga family data sheet rev. d 48 packaging information the pasic 3 product fami ly packaging informat ion is presented in table 32 . note: military temperature range plastic packages will be added as follow on products to the commercial and industrial products. ordering information table 32: packaging options device information device ql3004 ql3004e ql3006 ql3012 ql3025 ql3040 ql3060 pin pitch pin pitch pin pitch pin pitch pin pin pitch pin pitch pitch package definitions a a. plcc = plastic leaded chip carrier pqfp = plastic quad flat pack pbga = plastic ball grid array tqfp = thin quad flat pack 68 plcc 0.05 in. 68 plcc 0.05 in. 68 plcc 0.05 in. 84 plcc 0.05 in. 100 tqfp 0.5 mm 208 pqfp 0.5 mm 208 pqfp 0.5 mm 84 plcc 0.05 in. 84 plcc 0.05 in. 84 plcc 0.05 in. 100 tqfp 0.5 mm 144 tqfp 0.5 mm 456 pbga 1.27 mm 456 pbga 1.27 mm 100 tqfp 0.5 mm 100 tqfp 0.5 mm 100 tqfp 0.5 mm 144 tqfp 0.5 mm 208 pqfp 0.5 mm - - - - -------- 256 pbga 1.27 mm---- ql 3060 -1 pq208 c operating range: c = commercial i = industrial m = military package code: pl68 = 68-pin plcc pf84 = 84-pin plcc pf100 (pfn100)* = 100-pin tqfp pf144 (pfn144)* = 144-pin tqfp pq208 (pqn208)*= 208-pin pqfp pb256 (pbn256)*= 256-ball pbga pb456 (pbn456)*= 456-ball pbga part number: quicklogic device speed grade: 0 - quick 1 - fast 2 - faster 3 - faster 4 - wow** 3004, 3004e, 3006, 3012 3025, 3040, 3060 * lead-free packaging is available, contact quicklogic regarding availability (see contact information). ** contact quicklogic regarding availability (see contact information)
? 2005 quicklogic corporation www.quicklogic.com pasic 3 fpga family data sheet rev. d 49 contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history copyright and trademark information copyright ? 2005 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo, pasic, vialink, and quickworks are registered trademarks of quic klogic corporation; quicktools and spde are trademarks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. all trademarks and registered trademarks ar e the property of their respective owners. revision date comments a not avail. first release b june 2002 brian faith and andreea rotaru c march 2005 mehul kochar and kathleen murchek d september 2005 mehul kochar and kathleen murchek added lead free packaging information to ordering information section.

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